1. Field of the Invention
The present invention relates to a pad of a semiconductor device. More particularly, embodiments of the invention relate to a semiconductor pad having the same voltage level as that of an associated semiconductor substrate.
2. Discussion of Related Art
FIG. 1 illustrates a semiconductor device 100 having a plurality of pads 110 and a semiconductor chip 120. The semiconductor device 100 is electrically connected externally from the memory chip 120 using pads 110 and receives power needed to drive semiconductor chip 120, for example, a power voltage Vdd, a ground voltage Vss, and associated signals.
FIG. 2 is a sectional view of one of the pads 110 shown in FIG. 1. In particular, pad 200 of the semiconductor device 100 includes semiconductor substrate 210, a dummy pattern 220, a metal layer portion 230, a polylayer portion (PP) 240, and first and second insulation films 251 and 252. Dummy pattern 220 includes dummy gate poly 221 (GP) and dummy active 222 (Dum ACT). Metal layer portion 230 includes first metal layer 231 (M1), a second metal layer 232 (M2), and a third metal layer 233 (M3). First metal layer 231 receives an external voltage selectively and electrically connected to second metal layer 232 and third metal layer 233. First insulation film 251, polylayer portion 240, second insulation film 252, dummy gate poly 221, and dummy active 222 are located under third metal layer 233. These layers are formed as a dummy to have the same step as the peripheral area in semiconductor device 100 and reduce the stress generated during wire bonding between first metal layer 231 and a semiconductor pin (not shown). In the semiconductor device 100 configured as above, a particular voltage (Vss or Vdd) is applied by separately forming a plug to apply a bulk bias to semiconductor substrate 210 based on the substrate type. The applied voltage Vss or Vdd is used as a bulk bias of the semiconductor device which may be, for example, a transistor. Thus, a method is needed which provides an area of the semiconductor substrate 210 located under pad 200 to have the same voltage level as an externally applied voltage Vss or Vdd to utilize the area of the semiconductor substrate 210 as a plug to apply a bulk bias to the device.